1. Field of the Invention
The present invention relates mainly to a semiconductor device having an IIL (Integrated Injection Logic) circuit and a method of manufacturing the same.
2. Description of the Background Art
An IIL circuit is conventionally known as a saturation type logic circuit. The IIL circuit gives a simple circuit structure, low power consumption, and high density.
The IIL circuit will now be described briefly with reference to FIG. 20. FIG. 20 is an equivalent circuit diagram showing an example of the IIL circuit.
Referring to FIG. 20, the IIL circuit is configured of a lateral pnp transistor Q1 serving as current source, and a vertical npn transistor Q2 for operation as an inverter. The base region of pnp transistor Q1 serves also as the emitter region of npn transistor Q2. The collector region of pnp transistor Q1 serves also as the base region of npn transistor Q2. In the IIL circuit, plural collector regions may be formed in npn transistor Q2.
The operation of the IIL circuit shown in FIG. 20 will now be described. Referring again to FIG. 20, minority carriers are first injected from the emitter region into the base region of pnp transistor Q1. A large part of the minority carriers flows to a region serving both as the collector region of pnp transistor Q1 and the base region of npn transistor Q2. pnp transistor Q1 operates as a transistor whose base region is grounded.
On the other hand, when an input terminal IN connected to the base region of npn transistor Q2 is at a relatively high potential or in a floating state, npn transistor Q2 corresponding to the terminal is supplied at its base with the minority carriers from pnp transistor Q1 to be saturated. As a result, ground potential appears at an output terminal OUT. When the input terminal IN is at the ground potential (0 V), the minority carriers flow out from the input terminal IN. As a result, npn transistor Q2 is turned off.
Description will now be given of a cross sectional structure of a semiconductor device having such an IIL circuit as described above. FIG. 21 is a partial cross sectional view showing an example of a semiconductor device having a conventional IIL circuit. In the semiconductor device having an IIL circuit of FIG. 21, a field oxide film 106 is formed for isolating adjacent base regions 107. FIG. 22 is a partial cross sectional view of a semiconductor device having an IIL circuit in which adjacent base regions are isolated by an n.sup.+ emitter collar region 109.
Referring to FIG. 21, n type epitaxial layers 104, 104a are formed on the main surface of a p type semiconductor substrate 101. An n type buried layer 103 is formed in n type epitaxial layer 104a and in the main surface of p type semiconductor substrate 101. A p type buried isolation region 102 is formed so as to surround n type buried layer 103. A p type isolation region 105 is formed on p type buried isolation region 102.
Field oxide film 106 is selectively formed on the surface of n type epitaxial layers 104, 104a. A p type base region 107 is formed at a predetermined position between field oxide films 106. An n type collector region 108 is formed in the surface of p type base region 107.
Description will now be given of a semiconductor device having an IIL circuit in which n.sup.+ emitter collar region 109 isolates adjacent base regions 107, taken as a comparison example. Referring to FIG. 22, in the semiconductor device having an IIL circuit shown in the figure, n.sup.+ emitter collar region 109 rather than field oxide film 106 is formed at a predetermined region of the surface of n type epitaxial layer 104a. The semiconductor device shown in FIG. 22 is the same as the semiconductor device having an IIL circuit shown in FIG. 21.
In the semiconductor device having an IIL circuit shown in FIG. 22, since emitter collar region 109 is formed, it is possible to suppress the parasitic pnp effect between adjacent base regions 107. In addition to this, it is possible to reduce the width W between adjacent base regions 107, and to reduce an element in size.
The semiconductor device having an IIL circuit shown in FIG. 22 had, however, such problems as described below.
Referring again to FIG. 22, the above-described emitter collar region 109 is formed so as to be sandwiched by adjacent base regions 107. The concentration of emitter collar region 109 is 10.sup.9 -10.sup.20 cm.sup.-3, which is relatively high. Because of the concentration of emitter collar region 109, the concentration of epitaxial layer 104a between base regions 107 also becomes high. Therefore, the junction capacitance between epitaxial layer (emitter region) 104a and base region 107 increases, and the operation speed of the IIL circuit is lowered. This problem is described, for example, in the Journal of Institute of Electronics, Information and Communication Engineers of Japan of February, 1978.
On the other hand, in the structure shown in FIG. 21, since base regions 107 are isolated from each other only by field oxide film 106, the concentration of epitaxial layer 104a in the vicinity of base region 107 is suppressed. The junction area of base region 107 and epitaxial layer 104a is also small. As a result, the junction capacitance between base region 107 and epitaxial layer 104a can be suppressed, resulting in a semiconductor device having an IIL circuit having an improved operation speed. Furthermore, because of field oxide film 106, the parasitic pnp operation between base regions 107 can also be suppressed.
Because of the above, the structure shown in FIG. 21 in which base regions 107 are isolated from each other by field oxide film 106 is more preferable from the standpoint of performance.
In view of the above, description will now be given of a method of manufacturing the semiconductor device having an IIL circuit shown in FIG. 21 with reference to FIGS. 23 to 27. FIGS. 23 to 27 are cross sectional views showing the first to the fifth steps of the manufacturing process of the semiconductor device having an IIL circuit shown in FIG. 21.
Referring to FIG. 23, n type impurity region 103 is formed by introducing n type impurity into a predetermined region in the main surface of p type semiconductor substrate 101. Then, p type impurity region 102 is formed by introducing p type impurity into a predetermined region in the main surface of p type semiconductor substrate 101.
Referring to FIG. 24, n type epitaxial layers 104, 104a are formed on the main surface of p type semiconductor substrate 101 with an epitaxial growth method. Then, n type buried layer 103 and p type buried isolation region 102 are respectively formed. p type isolation region 105 is formed in n type epitaxial layers 104, 104a positioned on p type buried isolation region 102 using an ion implantation method or diffusion method.
Referring to FIG. 25, a silicon oxide film 111 and a silicon nitride film 112 are sequentially deposited on the entire surface of n type epitaxial layers 104, 104a using a CVD (Chemical Vapor Deposition) method or the like. A resist pattern 113 patterned into a predetermined shape is deposited on silicon nitride film 112. With resist pattern 113 used as a mask, silicon nitride film 112 is patterned. Then, resist pattern 113 is removed.
Referring to FIG. 26, with the above-described stacked structure of silicon oxide film 111 and silicon nitride film 112 used as a mask, field oxide film 106 is formed in the surface of n type epitaxial layers 104, 104a with an LOCOS (Local Oxidation of Silicon) method. The thickness of field oxide film 106 is approximately 1.5 .mu.m.
Referring to FIG. 27, with the above-described field oxide film 106 used as a mask, p type impurity such as boron (B) is implanted into the surface of n type epitaxial layers 104, 104a. As a result, p type base region 107 is formed.
By selectively introducing n type impurity such as arsenic (As) into the surface of base region 107, n type collector region 108 is formed in the surface of base region 107. The semiconductor device having an IIL circuit shown in FIG. 21 is thus formed.
In the semiconductor device having an IIL circuit shown in FIG. 21, however, there was such a problem as described below. Referring again to FIG. 21, when base regions 107 are isolated from each other by field oxide film 106, the isolation width W1 between base regions 107 is determined by the parasitic pnp operation (parasitic bipolar operation) between adjacent base regions 107. More specifically, the width W1 between base regions 107 is determined so that the parasitic pnp operation will not occur. As a result, it becomes difficult to reduce the width W1 between base regions 107, which hampers reduction of a semiconductor device having an IIL circuit in size.